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IDT74FCT841A/B HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
COMMERCIAL TEMPERATURE RANGE
HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
FEATURES: DESCRIPTION:
IDT74FCT841A/B
* Equivalent to AMD's Am29841 bipolar registers in pinout/ function, speed, and output drive over full temperature and voltage supply extremes * IDT74FCT841A equivalent to FASTTM speed * IDT74FCT841B 25% faster than FAST * Buffered common latch enable, clear and present inputs * IOL = 48mA * Clamp diodes on all inputs for ringing suppression * CMOS power levels (1mW typ. static) * TTL input and output level compatible * CMOS output level compatible * Substantially lower input current levels than AMD's bilopar Am29800 series (5A max.) * Available in SOIC package
The IDT74FCT800 series is built using an advanced dual metal CMOS technology. The IDT74FCT840 series bus interface latches are designed to eliminate the extra packages required to buffer existing latches and provide extra data width for wider address/data paths or buses carrying parity. The IDT74FCT841 is a buffered, 10-bit wide version of the popular `373 function. All of the IDT74FCT800 high-performance interface family are designed for high-capacitance load drive capability, while providing low-capacitance bus loading at both inputs and outputs. All inputs have clamp diodes and all outputs are designed for low-capacitance bus loading in the high-impedance state.
FUNCTIONAL BLOCK DIAGRAM
D0
D1
D2
D3
D4
D5
D8
D9
D Q LE
D Q LE
D Q LE
D Q LE
D Q LE
D Q LE
D Q LE
D Q LE
LE
OE Y0 Y1 Y2 Y3 Y4 Y5 Y8 Y9
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
JUNE 2002
DSC-4603/4
(c) 2002 Integrated Device Technology, Inc.
IDT74FCT841A/B HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
OE D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 LE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VTERM(2) VTERM(3) TA TBIAS TSTG PT IOUT Description Terminal Voltage with Respect to GND Terminal Voltage with Respect to GND Operating Temperature Temperature under BIAS Storage Temperature Power Dissipation DC Output Current Max -0.5 to +7 -0.5 to VCC 0 to +70 -55 to +125 -55 to +125 0.5 120 Unit V V C C C W mA
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed Vcc by +0.5V unless otherwise noted. 2. Input and Vcc terminals only. 3. Output and I/O terminals only.
CAPACITANCE (TA = +25C, F = 1.0MHz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. 10 12 Unit pF pF
SOIC TOP VIEW
NOTE: 1. This parameter is measured at characterization but not tested.
PIN DESCRIPTION
Pin Names Dx LE I/O I I Description Latch Data Inputs Latch Enable Input. The latches are transparent when LE is HIGH. Input data is latched on the HIGH-toLOW transition. 3-State Latch Outputs Output Enable Control. When OE is LOW, the outputs are enabled. When OE is HIGH, the outputs Yx are in high-impedance (off) state.
FUNCTION TABLE(1)
OE H H H H L L L H H Inputs LE X H H L H H L L L Dx X L H X L H X X X Internal Qx X L H NC L H NC L H Output Yx Z Z Z Z L H NC Z Z Function High Z High Z High Z Latched (High Z) Transparent Transparent Latched Latched (High Z) Latched (High Z)
Yx OE
O I
NOTE: 1. H = HIGH Voltage Level X = Don't Care L = LOW Voltage Level Z = High-Impedance NC = No Change
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IDT74FCT841A/B HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: VLC = 0.2V; VHC = VCC - 0.2V Commercial: TA = 0C to +70C, VCC = 5.0V 5%
Symbol VIH VIL IIH IIL IOZH IOZL VIK IOS VOH Off State (High Impedance) Output Current Clamp Diode Voltage Short Circuit Current Output HIGH Voltage VCC = Max. Parameter Input HIGH Level Input LOW Level Input HIGH Current VCC = Max. Input LOW Current Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VI = VCC VI = 2.7V VI = 0.5V VI = GND VO = VCC VO = 2.7V VO = 0.5V VO = GND Test Conditions(1) Min. 2 -- -- -- -- -- -- -- -- -- -- -75 VHC VHC 2.4 -- -- -- Typ.(2) -- -- -- -- -- -- -- -- -- -- -0.7 -120 VCC VCC 4.3 GND GND 0.3 Max. -- 0.8 5 5(4) -5(4) -5 10 10(4) -10(4) -10 -1.2 -- -- -- -- VLC VLC(4) 0.5 A A Unit V V
VCC = Min., IIN = -18mA VCC = Max., VO = GND(3) VCC = 3V, VIN = VLC or VHC, IOH = -32A VCC = Min IOH = -300A VIN = VIH or VIL IOH = -24mA VCC = 3V, VIN = VLC or VHC, IOL = 300A VCC = Min IOL = 300A VIN = VIH or VIL IOL = 48mA
V mA V
VOL
Output LOW Voltage
V
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient and maximum loading. 3. Not more than one output should be tested at one time. Duration of the test should not exceed one second. 4. This parameter is guaranteed but not ttested.
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IDT74FCT841A/B HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
COMMERCIAL TEMPERATURE RANGE
POWER SUPPLY CHARACTERISTICS
VLC = 0.2V; VHC = VCC - 0.2V
Symbol ICC ICC ICCD Parameter Quiescent Power Supply Current Quiescent Power Supply Current TTL Inputs HIGH Dynamic Power Supply Current(4) Test Conditions(1) VCC = Max. VIN VHC; VIN VLC VCC = Max. VIN = 3.4V(3) VCC = Max. Outputs Open OE = GND LE = VCC One Input Toggling 50% Duty Cycle VCC = Max. Outputs Open fi = 10MHz 50% Duty Cycle OE = GND LE = VCC One Bit Toggling VCC = Max. Outputs Open fi = 2.5MHz 50% Duty Cycle OE = GND LE = VCC Eight Bits Toggling VIN VHC VIN VLC Min. -- -- -- Typ.(2) 0.2 0.5 0.15 Max. 1.5 2 0.25 Unit mA mA mA/ MHz
IC
Total Power Supply Current(6)
VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND
--
1.7
4
mA
--
2
5
VIN VHC VIN VLC (FCT) VIN = 3.4V VIN = GND
--
3.2
6.5(5)
--
5.2
14.5(5)
NOTES: 1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at VCC = 5.0V, +25C ambient. 3. Per TTL driven input (VIN = 3.4V). All other inputs at VCC or GND. 4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations. 5. Values for these conditions are examples of ICC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ICC DHNT + ICCD (fCP/2 + fiNi) ICC = Quiescent Current ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current caused by an Input Transition Pair (HLH or LHL) fCP = Clock Frequency for register devices (zero for non-register devices) fi = Input Frequency Ni = Number of Inputs at fi All currents are in milliamps and all frequencies are in megahertz.
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IDT74FCT841A/B HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
COMMERCIAL TEMPERATURE RANGE
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
74FCT841A Symbol tPLH tPHL Parameter Propagation Delay Dx to Yx (LE = HIGH) Condition(1) CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 50pF RL = 500 CL = 300pF(4) RL = 500 CL = 5pF(4) RL = 500 CL = 50pF RL = 500 CL = 50pF RL = 500 Min.(2) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4 Max. 9 13 12 16 11.5 23 7 18 -- -- -- Min.(2) 1.5 1.5 1.5 1.5 1.5 1.5 1.5 1.5 2.5 2.5 4 74FCT841B Max. 6.5 13 8 15.5 8 14 6 7 -- -- -- ns ns ns ns ns ns Unit ns
tPLH tPHL
Propagation Delay LE to Yx
tPZH tPZL
Output Enable Time, OE to Yx
tPHZ tPLZ
Output Disable Time, OE to Yx
tSU tH tW
Data to LE Set-up Time Data to LE Hold Time LE Pulse Width HIGH(3)
NOTES: 1. See test circuit and waveforms. 2. Minimum limits are guaranteed but not tested on Propagation Delays. 3. These parameters are guaranteed but not tested. 4. This condition is guaranteed but not tested.
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IDT74FCT841A/B HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
COMMERCIAL TEMPERATURE RANGE
TEST CIRCUITS AND WAVEFORMS
V CC 500 VIN Pulse Generator RT D.U.T . VOUT 7.0V
SWITCH POSITION
Test Open Drain Disable Low Enable Low Switch Closed Open
50pF CL
500
All Other Tests
DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
Octal link
Test Circuits for All Outputs
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL PRESET CLEAR ETC. SYNCHRONOUS CONTROL PRESET CLEAR CLOCK ENABLE ETC.
tSU
tH
tREM
3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V 3V 1.5V 0V
Octal link
LOW-HIGH-LOW PULSE tW HIGH-LOW-HIGH PULSE
Octal link
1.5V
1.5V
tSU
tH
Pulse Width
Set-Up, Hold, and Release Times
ENABLE SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH OPPOSITE PHASE INPUT TRANSITION tPHL tPHL 3V 1.5V 0V VOH 1.5V VOL 3V 1.5V 0V
Octal link
DISABLE 3V 1.5V 0V 3.5V 0.3V tPHZ 0.3V 1.5V 0V VOH 0V
Octal link
CONTROL INPUT tPZL OUTPUT NORMALLY LOW OUTPUT NORMALLY HIGH SWITCH CLOSED tPZH SWITCH OPEN 3.5V 1.5V tPLZ
VOL
Propagation Delay
Enable and Disable Times
NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH. 2. Pulse Generator for All Pulses: Rate 1.0MHz; ZO 50; tF 2.5ns; tR 2.5ns.
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IDT74FCT841A/B HIGH-PERFORMANCE CMOS BUS INTERFACE LATCH
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
IDT XX XXXX FCT Temp. Range Device Type X Package
SO
Small Outline IC
841A 841B
Bus Interface Latch
74
0C to +70C
DATA SHEET DOCUMENT HISTORY
6/27/2002 Updated according to PDNs Logic-00-07 and Logic-01-04
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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